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CAT24C21
Table 5. A.C. CHARACTERISTICS (V CC = 2.5 V to 5.5 V, unless otherwise specified. Industr ial temperature range.)
Symbol
Parameter
Min
Max
Units
TRANSMIT ? ONLY MODE
T VAA
T VHIGH
T VLOW
T VHZ
T VPU
Output valid from VCLK
VCLK high
VCLK low
Mode transition
Transmit ? only power ? up
0.6
1.3
0
0.5
0.5
m s
m s
m s
m s
ns
READ & WRITE CYCLE LIMITS
F SCL
T I (Note 8)
t AA
t BUF (Note 8)
t HD:STA
t LOW
t HIGH
t SU:STA
t HD:DAT
t SU:DAT
t R (Note 8)
t F (Note 8)
t SU:STO
t DH
Clock Frequency
Noise Suppression Time Constant at SCL, SDA Inputs
SCL Low to SDA Data Out and ACK Out
Time the Bus Must be Free Before a New Transmission Can Start
Start Condition Hold Time
Clock Low Period
Clock High Period
Start Condition Setup Time
Data In Hold Time
Data In Setup Time
SDA and SCL Rise Time
SDA and SCL Fall Time
Stop Condition Setup Time
Data Out Hold Time
1.2
0.6
1.2
0.6
0.6
0
50
0.6
100
400
100
1
0.3
300
kHz
ns
m s
m s
m s
m s
m s
m s
ns
ns
m s
ns
m s
ns
POWER ? UP TIMING (Note 8 and 9)
t PUR
t PUW
Power ? up to Read Operation
Power ? up to Write Operation
1
1
ms
ms
WRITE CYCLE LIMITS
t WR
Write Cycle Time
5
ms
8. This parameter is tested initially and after a design or process change that affects the parameter.
9. t PUR and t PUW are the delays required from the time V CC is stable until the specified operation can be initiated.
The write cycle time is the time from a valid stop condition
of a write sequence to the end of the internal program/erase
cycle. During the write cycle, the bus interface circuits are
disabled, SDA is allowed to remain high, and the device
does not respond to its slave address.
Pin Description
The SCL serial clock input pin is used to clock all data
transfers into or out of the device when in the bi ? directional
mode.
The SDA bi ? directional serial data/address pin is used to
transfer data into and out of the device. The SDA pin is an
open drain output and can be wire ? ORed with other open
drain or open collector outputs.
Functional Description
The CAT24C21 has two modes of operation: the
transmit ? only mode and the bi ? directional mode. There is a
separate 2 ? wire protocol to support each mode, each having
a separate clock input (VCLK and SCL respectively) and
both modes sharing a common bi ? directional data line
(SDA). The CAT24C21 enters the transmit ? only mode upon
power up and begins outputting data on the SDA pin with
each clock signal on the VCLK pin. The device will remain
in the transmit ? only mode until there is a valid HIGH to
LOW transition on the SCL pin, when it will switch to the
bi ? directional mode (Figure 2). Once in the bi ? directional
mode, the only way to return to the transmit ? only mode is
by powering down the device.
The VCLK serial clock input pin is used to clock data out
of the device when in transmit ? only mode. When held low,
in bi ? directional mode, it will inhibit write operations.
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